1. Field
Exemplary embodiments of the present invention relate to an analog-to-digital converter (ADC) and an analog-to-digital (AD) conversion method using the same.
2. Description of the Related Art
Most systems currently used are designed based on a digital signal processing technique. In this regard, the role of an analog-to-digital converter, which is an initial step of digital signal processing, is important.
FIG. 1 is a configuration diagram illustrating a part of a conventional ADC.
As illustrated in FIG. 1, the ADC includes a comparator 110 and 1st to Nth capacitors C1 to CN (FIG. 1 shows 6 capacitors).
The comparator 110 outputs a comparison result between a comparison voltage VCMP and an input voltage IN, which corresponds to each bit of a digital signal AD converted from an input signal sampled to the input node IN.
One end of each of the 1st to Nth capacitors C1 to CN is connected to the input node IN, and the other ends of the capacitors C1 to CN receive one of an input signal, the comparison voltage VCMP, and one or more reference voltages. Since the capacitances of the capacitors C1 to CN have a weighted value, a capacitance of a Kth (2≦K≦N) capacitor of the capacitors C1 to CN is generally 2^(N−K−1) times as large as a capacitance of the Nth capacitor.
In a sampling step, the input signal is applied to the other ends of the capacitors C1 to CN, so that the capacitors C1 to CN are charged and the input signal is sampled.
In a conversion step, one of the one or more reference voltages is applied to the other ends of the capacitors C1 to CN according to the comparison result of the comparator 110. When the conversion step is completed, a reference voltage applied to the other ends of the capacitors C1 to CN determines a value of each bit of the digital signal AD converted from the input signal.
In general, conversion from an input signal into a N-bit digital signal needs N capacitors, and N−1 voltage selection units, which select a voltage to be applied to N−1 capacitors (the comparison voltage VCMP is applied to the other end of the Nth capacitor CN), and a control unit 120 that generates a control signal for controlling the N−1 voltage selection units.
As the value of N is increased, resolution is increased and thus a digital signal has a digital value more approximate to a value of an actual input signal. However, according to the conventional ADC, as increase of resolution needs more capacitor and the control unit 120, the conventional ADC is required to have a significant increase in a circuit area. For example, when the resolution is increased twice, the number of the capacitors should be increased twice, capacities of added capacitors also should be increased twice, and thus areas for the capacitors should be increased more than twice as the original resolution. Furthermore, as the number of signals for controlling a switching unit (S1 to S5) for selecting a voltage to be applied to the other end of the capacitor should be increased twice as before the original resolution, the area for the control unit 120 also should be increased more than twice.
Therefore, doubled increase of the resolution requires more than doubled area of the ADC, which leads to serious increase of power consumption and limits improvement of the resolution.